发明名称 Sample-and-hold circuit
摘要 A sample-and-hold circuit is provided with a plurality of first capacitors, respectively connected to a plurality of input signal lines through respective first analog switches, for sampling input signal voltages, a plurality of second capacitors, respectively connected to the plurality of first capacitors through respective second analog switches, for holding the sampled voltages, and a single operational amplifier for selectively receiving one of the voltages held in the plurality of second capacitors according to a control signal supplied thereto, and amplifying and outputting the received voltages.
申请公布号 US5304866(A) 申请公布日期 1994.04.19
申请号 US19920868213 申请日期 1992.04.14
申请人 SHARP KABUSHIKI KAISHA 发明人 URANAKA, SHINICHI
分类号 G09G3/18;G11C27/02;(IPC1-7):H03K5/159;H03K5/153 主分类号 G09G3/18
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