| 摘要 |
<p>PURPOSE:To suppress the increase of a chip area to the minimum and to improve cost performance by optimizing the allocation and the division in the column direction of the number of bits read from each memory cell. CONSTITUTION:A memory cell array 131 is composed of 512 memory cells in the column direction and 4096 in the row direction and a memory cell array 132 is composed of 768 memory cells in the column direction and 4096 in the row direction. One of plural word lines made to be the state capable of selection by means of a selection signal for a first row from a decoder 11 is selected and driven by means of a selection signal for a second row from a second row decoder. The outputs of respective sense amplifiers 18 have two or three bits according to the bit width in the column direction of the corresponding memory cell array and data of 16 bits are outputted in all. Namely, respective column selection circuits 17 select two bits from among 512 bits in the column direction or three bits among 768 bits in the column direction by means of a column selection signal from a column decoder 19 and output these bits to a sense amplifier 18.</p> |
