| 摘要 |
PURPOSE:To provide the controller for bit operation in CPU which accelerates bit operation whith reduced hardware. CONSTITUTION:Data set to a register in a general-purpose register file 4 are supplied to connection switching circuits 6a and 6b. When the inversion of a bit position is deisgnated, corresponding to the previously set value of a flag register 5, the data of respective registers are supplied to register selecting circuits 7a and 7b by the connection switching circuits 6a and 6b while inverting the bit positions. The register selecting circuits 7a and 7b select registers one by one, and the data inverted the bit positions are outputted to internal buses 1 and 2. An ALU 8 fetches the data on the internal buses 1 and 2, performs the arithmetic operation and outputs the arithmetic result to an internal bus 3. |
