| 摘要 |
The number of zeroes in an operation result of 54 bits is counted by a priority encoder 2 on a three-bit basis. A 54*18 normalization shifter 3 normalizes the operation result in response to the counted result. An LSB determination logic 4 determines a position of the LSB shifted by overflow and underflow, according to a logic state of the most significant three bits of the operation result, and an increment signal generating portion 5 and a three-bit input incrementer 6 add 1 corresponding to the shifted LSB to generate a round-up signal. A 54*3 normalization shifter 9 selectively normalizes a processed result of a lost-significant bit processing portion B or that of a round processing portion A. Normalization shifters of the lost-significant bit processing portion constitute a two stage structure, in which the normalization shifter in the final stage also serves for the rounding processing portion, and a normalization shifter in the succeeding stage of an arithmetic operation portion is omitted. Consequently, a floating point arithmetic unit with the reduced volume of hardware can be provided without reducing the operation speed.
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