| 摘要 |
<p>PURPOSE:To reduce the capacity of a buffer memory circuit operating at a high speed by providing a rearranging circuit to be operated at the speed lower than that of the buffer memory while receiving the output of the buffer memory and to provide a required synchronizing signal. CONSTITUTION:A lower-order group signal 7 is inputted to a buffer memory circuit 30, and a lower-order group write clock 8 is inputted to a circuit 1 and a phase comparator 4. On the other hand, a synchronizing clock pulse 9 is outputted from a synchronized clock oscillator 2. A read clock generating circuit 3 receives the pulse 9 and outputs a synchronizing clock signal 10. A stuff control circuit 5 inputs the signal 10 and when a stuff requesting signal from the phase comparator 4 is significant, a read clock signal 12 is outputted by performing pulse stuffing. Corresponding to the signal 12, the circuit 1 outputs a synchronizing signal 13. A rearranging circuit 6 is provided with the large capacitor buffer, inputs the signal 13, rearranges data so as to satisfy the frame format of the CCITT recommendation and outputs the data as a synchronizing signal 14.</p> |
