| 摘要 |
PURPOSE:To provide the memory control circuit for improving a service life of a memory by minimizing the number of times of rewriting of an EEPROM by making a gate for transferring SRAM data to the EEPROM active, only when a power source of an apparatus is cut off in the case the SRAM data is changed, at the time of changing the data of the memory in which the SRAM and the EEPROM are integrated in one chip. CONSTITUTION:The memory control circuit is constituted so that at the time of transferring data from an EEPROM to an SRAM, or from the SRAM to the EEPROM in a memory in which the SRAM and the EEPROM are integrated in one chip, data 1b of the EEPROM to the SRAM at the time when a power source is turned on, by monostable multivibrator circuits 6, 7 and a RAM data change deciding circuit 11 operated in accordance with an output of a voltage detecting circuit 8 for detecting turn-on and cut-off of a power source of an apparatus, and also, SRAM data 1a is transferred to the EEPROM only when the SRAM data 1a is changed and the power source is cut off, and a backup circuit 5 for secuting the power source by the time required for a transfer time is provided. |
