Processor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte

摘要

A processor array (2) employs an SIMD architecture and includes a number of single-bit processor elements. Each processor element includes an arithmetic unit (ALU) and at least one operand register (Q) for the arithmetic unit (ALU). Each processor element (PE) further includes a multi-byte bit-wise shift register. Data outputs are formed in said shift register for each byte position. Data is communicated from a selected one of the outputs to the arithmetic unit via a multiplexer (Z-MUX). In one example, the shift register is unidirectional and includes a cyclical data path which connects the least significant bit of the register to the most significant end. The register may output data from one of the outputs and shift data cyclically from the most significant to the least significant end in a single operation.