| 摘要 |
A processing module for performing an operation of the type B=a.X+T in which B, X and T are high value integers, and a is an operand having a format restricted to m bits, in sequences constituted from computing steps consisting in combining the operand a with operands xi and ti, of restricted format, extracted from the data X and T, at the rank of significance i and in storing a partial result bi of the same significance rank, this processing module including a static multiplier and two adders and a resistor for storing and recycling the most significant portion of a previous computing step. The processing module includes k inputs for operands a (l . . . k) of successive ranks, for successively applying, in work cycles k steps the said operands a (l . . . k) to one of the inputs of the multiplier, registers and multipliers enabling a delay of k computing steps in the most significant portion of the result at the output of a second adder and of (k-1) computing steps in the least significant portion of the same result, respectively in the first step and in the other steps of each cycle.
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