摘要 |
The interface circuit uses a memory buffer (10,20,30,40) connected between the processor data bus (4) and the parallel port of a data conversion register (16,36) of which the serial port is connected to the peripheral device (3). A counter (80) generates a primary address (TADD,RADD) and a primary memory access signal (TRRW) driving a selector circuit (60,70) which receives a second address (PADD) and a second memory access signal (PWR,PRD) from the processor. On receiving a signal, the selector circuit(60,70) directs the addresses and control signals to the buffer (10,20,30,40). ADVANTAGE - Serial communication between processor and peripherals with improved transmission rate due to reduction of redundant blocks.
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