发明名称 CLOCK SYNCHRONIZATION SYSTEM
摘要 <p>PURPOSE:To continue communication stably even when a gateway being a supply port of a clock is revised by providing a phase comparator in a phase locked loop on a gateway connecting to an external network and providing a loop filter and a voltage controlled oscillator on other node being a clock master node. CONSTITUTION:In the system where a network comprising plural networks through interconnection is operated synchronously with a clock signal fed from other network, a clock signal coming from an external network is extracted by gateways 2a, 2b normally and phase difference information is obtained by a phase comparator. When a decoder of a clock master node 1g extracts only phase difference information from some one gateway 2a and aborts other information and when the selected phase difference information is not received due to interruption of a transmission line or the like, the information from the other gateway 2b this far aborted thus is selected and a voltage controlled oscillator is controlled.</p>
申请公布号 JPH0629987(A) 申请公布日期 1994.02.04
申请号 JP19920178567 申请日期 1992.07.06
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 SHIMIZU TOSHIYUKI;KISHIMOTO HIDEO;YOKOTA NAGANARI;HAKAMATA YOSHIRO
分类号 H04J3/06;H04L7/027;(IPC1-7):H04L12/28;H04L12/40;H04L12/42;H04L12/44 主分类号 H04J3/06
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