发明名称 ADDER
摘要 PURPOSE:To realize addition by an analog value by inputting one output of an arithmetic amplifier to the output-side reference voltage terminal of the other arithmetic amplifier, executing addition by the analogue value and digitally judging whether an addition result including carry-in is carry-processed or not. CONSTITUTION:An inverted input terminal IBO and a reference voltage OBO in the basic element BD2 of an adder M are grounded and the arithmetic result of (A+B) is obtained in the output terminal OA2 of the basic element BD1. The arithmetic result is inputted to comparators C1 and C2, and it is compared with the cardinal number N of addition and (N-1). The carry-in C as against the adder is inputted to a computing element CAL with a G-flag and a P-flag, and output SUB is decided. Output SUB is inputted to an arithmetic circuit consisting of reference elements BD3 and BD4, and operation for subtracting SUB from (A+B) is executed and final output S is calculated. The analog adder of a carry-look-ahead type is obtained.
申请公布号 JPH0628503(A) 申请公布日期 1994.02.04
申请号 JP19920148468 申请日期 1992.05.15
申请人 TAKAYAMA:KK;SHARP CORP 发明人 UIWATSUTO UONWARAUIPATSUTO;YOU IKOU;YAMAMOTO MAKOTO
分类号 G06F7/49;G06G7/14;(IPC1-7):G06G7/14 主分类号 G06F7/49
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