发明名称 Verfahren zum Herstellen einer Modul-Halbleiter-Leistungsanordnung und hergestellte Anordnung.
摘要 The components used in the method comprise a heat-dissipating base plate, one or more three-layer plates (the top layer consisting of copper plates, and strips) and a one-piece frame designed to constitute the terminals (81-87). After the chips have been soldered onto the upper plates and connected to the strips, the inner ends of the frame are soldered to points of connection with the chips. This is followed by the encapsulation in resin and the shearing of the outer portions of the frame, which, during the process, serve to temporarily connect the terminals.
申请公布号 DE3884019(T2) 申请公布日期 1994.02.03
申请号 DE19883884019T 申请日期 1988.02.29
申请人 SGS-THOMSON MICROELECTRONICS S.R.L., AGRATE BRIANZA, MAILAND/MILANO, IT 发明人 PERNICIARO, SPATRISANO ANTONIO, I-90144 PALERMO PA, IT;MINOTTI, CARLO, I-95121 CATANIA CT, IT;GANDOLFI, LUCIANO, I-20094 CORSICO MI, IT;DI CRISTINA, NATALE, I-95145 PALERMO PA, IL
分类号 A61K39/175;C12N7/06;H01L21/50;H01L23/495;H01L25/065;(IPC1-7):H01L25/04;H01L23/52 主分类号 A61K39/175
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