Voltage generator circuit for dynamic random access memory - has inverters connected via capacitors to NMOS and PMOS field effect transistors

摘要

The circuit includes inverters (1,2) for producing two complementary clock signals. A capacitor (3) is connected to receive the first clock signal on one electrode. A field effect transistor (8) has its source connected to the other electrode of the capacitor, and the drain connected to the output node. A second capacitor receives the second clock signal on one electrode. A second field effect transistor (6) has its gate connected to the other electrode of the second capacitor, and is connected between the source of the first FET and the supply voltage. The FETs are of different conductivity types. The gate of the first is connected to the second electrode of the second capacitor. USE/ADVANTAGE - For substrate bias voltage generating in semiconductor DRAM using MOSFETs. Does not produce drop in output voltage at threshold voltage of transistors.