High speed BiCMOS memory having large noise margin and repeatable read port

摘要

A memory that is comprised of an array of memory cells which are made of cross-coupled field effect transistors further has a novel read port to read data from the cells. This read port includes a) a respective P-channel transistor for each memory cell having a gate coupled to a set or reset node of the cell; b) each P-channel transistor in a row of memory cells has a drain coupled to a respective row line for the row of cells which is otherwise disconnected from the cells; c) each P-channel transistor has a source coupled to the base of a respective bipolar transistor; and, d) each bipolar transistor in a column of memory cells has a collector coupled to a voltage bus and has an emitter coupled via a bit line to a sense amplifier for the column. With this read port structure "1" and "0" data bits can be read from the cells with both a high speed and a high noise margin. Any number of additional read ports can be provided by simply duplicating the components a) thru d) for each such port.