| 摘要 |
PURPOSE:To simplify a circuit scale, and to attain the high speed of an arithme tic speed. CONSTITUTION:This circuit is equipped with a booth decode circuit 1 which inputs multipliers (Yj-1, Yj, and Yj+1), and prepares decode outputs TW, PU, and Z, and a partial product preparing circuit 6 which inputs the decode outputs and multiplicands (Xi, and Xi-1), and prepares a partial product. Especially, the scale of the circuit 1 is reduced, and the number of stages of gates is decreased. The TW output of the circuit 1 is prepared by inverting the EX-OR of the multiplier inputs Yj and Yj-1, the PU output is prepared by inverting the multiplier Yj+1, and the Z output is prepared by operating the logical product of the inversion of the EX-OR of the Yj+1 and Yj, and the inversion of the EX-OR of the EX-OR of the Yj and Yj-1. Also, the output PP of the circuit 6 is prepared by operating the logical product of the logical product of the TW inversion and the Xi, and the logical product of the TW and the Xi-1, inverting the EX-OR of the pertinent logical product and the PU, and inverting the logical sum of the obtained result and the Z. |
