| 摘要 |
<p>PURPOSE: To attain miniaturization and cost reduction by connecting a memory cell to a sense amplifier through a switch capable of independent acuation, and thereby speeding up access to a central processing unit or a high memory level. CONSTITUTION: When a memory cell 10 forms the entirety or a part of cache memory, a first and a third memory cell 10A, 10C are made a first block, while a second and a fourth memory cell 10B, 10D a second block. In this case, an address decoder selects either to independently access the first and the third switch 36, 44, connecting to sense amplifiers 32, 34 only the memory cell in the first block, or to independently actuate the first and the fourth switch 36, 48, thereby connecting to the sense amplifiers 32, 34 the memory cells existing both in the first and second blocks. Thus, access is attained at high speed.</p> |
