Centralized backplane bus arbiter for multiprocessor systems

摘要

An Arbiter (36) is coupled to a multiprocessor system (10) Global Bus (24) having two separate main buses: an address bus (ABUS) and a data bus (DBUS). Bus agents coupled to the Global Bus request access to use the buses by asserting bus request lines to the Arbiter. The Arbiter is a dual level, round robin Arbiter that employs a fast, single-cycle arbitration technique. During each system clock cycle, the Arbiter considers the signals on the request input lines and generates corresponding grant output lines which dictate, for the next cycle, which bus agent is to receive access to the address bus and which bus agent is to receive access to the data bus.