发明名称 |
NAND-cell type electrically erasable and programmable read-only memory with redundancy circuit |
摘要 |
A NAND-cell type electrically erasable and programmable read only memory includes an array of rows and columns of memory cells associated with parallel bit lines on a semiconductive substrate. Each memory cell essentially consists of a floating-gate field effect transistor having a floating gate and an insulated control gate. The memory cell array is divided into a plurality of cell blocks, each of which includes NAND cell sections each including a predetermined number of a series-connected memory cell transistors. A redundancy cell section is provided which includes an array of redundancy memory cells containing at least one spare cell block. A row redundancy circuit is connected to a row decoder, and is responsive to an address buffer. The redundancy circuit replaces a defective block containing a defective memory cell or cells with the spare cell block. |
申请公布号 |
US5278794(A) |
申请公布日期 |
1994.01.11 |
申请号 |
US19920960882 |
申请日期 |
1992.10.14 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
TANAKA, YOSHIYUKI;ITOH, YASUO;MOMODOMI, MASAKI;IWATA, YOSHIHISA;TANAKA, TOMOHARU |
分类号 |
G11C17/00;G11C16/04;G11C16/06;G11C29/00;G11C29/04;(IPC1-7):G11C11/40;G11C5/02 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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