发明名称 Variable sized FIFO memory and programmable trigger level therefor for use in a UART or the like
摘要 Apparatus for providing data available interrupts that have a variable threshold for reading data from a receiver FIFO, and for selecting the depth of a variable depth FIFO for use as either the receiver or transmitter FIFO of a UART. The interrupt circuit determines if the FIFO data level is at or exceeds a preselected threshold value, and if it doesn't, triggers the reduction of the threshold level after a preselected period of time if there has been no access of the FIFO. If the data available level is still less than the reduced threshold value, the threshold value is again reduced by a preselected value following each elapse of a second preselected pause between each resetting of the threshold level until either a data available interrupt occurs, the threshold level is dropped to zero, or the FIFO is accessed. Whenever the receiver FIFO is accessed, the threshold level is reset to the original preselected level. The variable depth FIFO has a plurality of storage locations, and the depth of the storage locations is selected from fewer storage locations than the maximum number to the maximum number of the storage locations.
申请公布号 US5278956(A) 申请公布日期 1994.01.11
申请号 US19900468041 申请日期 1990.01.22
申请人 VLSI TECHNOLOGY, INC. 发明人 THOMSEN, JOSEPH A.;LONG, MARTY L.
分类号 G06F5/10;G06F13/24;G06F13/38;(IPC1-7):G06F3/00 主分类号 G06F5/10
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