Memory column address strobe buffer and synchronization and data latch interlock

摘要

A buffer and synchronization circuit for a computer system which provides synchronization of the column address strobe (CAS) signals provided to the memory DRAMs and which interlocks the memory data latch enable with the CAS signals provided from the memory controller without adding extra clock cycles or wait states. A synchronized buffer circuit receives the CAS signals from the memory controller and provides a plurality of synchronized duplicate CAS signals to the memory DRAMs. The synchronized buffer circuit includes several gate drivers in a single semiconductor chip so that each of the drivers has approximately the same delay in order to minimize skew between the duplicated CAS signals. An interlocking buffer circuit receives the memory data latch enable signal and the CAS signals from the memory controller and provides a synchronized memory latch enable to the data buffers. The buffer and synchronization circuit according to the present invention interlocks the memory latch enable to the CAS signals so that the latch enable is not negated prematurely regardless of the premature negation of the memory data latch enable from the memory controller.