发明名称 Hardware semaphores in a multi-processor environment
摘要 In a computer system having at least two processors, each processor having an associated memory, the processors being coupled to one another through an interface unit by means of a bus, hardware semaphores to regulate access to shared resources are disclosed. Each semaphore is one bit wide and can be written to obtain the desired state. When reading the semaphore, if the contents is a one, then a one is returned. If the content is zero, a zero is returned but the semaphore is automatically reset to one.
申请公布号 US5276886(A) 申请公布日期 1994.01.04
申请号 US19900596101 申请日期 1990.10.11
申请人 CHIPS AND TECHNOLOGIES, INC. 发明人 DROR, ASAEL
分类号 G06F13/14;G06F15/167;(IPC1-7):G06F13/14;G06F15/16 主分类号 G06F13/14
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