| 摘要 |
PURPOSE:To obtain the data demodulator for a DPSK signal realized by a digital circuit only and implementing symbol synchronization and correction of frequency shift. CONSTITUTION:The data demodulator uses a phase detection means 101, a delay means 102 and a phase difference detection means 103 to produce a phase difference signal p3 resulting from applying delay detection to a pi/4 QPSK signal (r) synchronously with a clock signal clk and uses a discrimination means 104 to reproduce the phase difference signal p3 into discrimination data d1. A discrimination error square means 112 obtains a discrimination error ea from the phase difference signal p3 and the discrimination data d1. A signal processing means 107A or the like based on the discrimination error ea calculates a proper sampling phase s1 of the discrimination data d1. A sampling means 111 samples the discrimination data d1 in a timing of the sampling phase s1 to obtain demodulation data d2 with symbol synchronization. |
