| 摘要 |
PURPOSE:To miniaturize the circuit and to reduce energy consumption by comparing the output bits of parallel/serial(P/S) converters for synchronizing patterns and received data with respectively correspondent converters and judging whether synchronizing patterns are detected or not corresponding to the number of coincident/noncoincident bits. CONSTITUTION:After performing S/P-conversion of received data by an S/P conversion circuit 31, the data are n-divided and respectively inputted to the (n) pieces of P/A converters 34-1-34-n for received data. On the other hand, the output synchronizing pattern of a synchronizing pattern designating register 32 is n-divided and respectively inputted to the (n) pieces of P/S converters 33-1-33-n for synchronizing pattern. A plural-bit comparator 35 compares the output bits of the converters 35-1-35-n and 34-1-34-n with the corresponding converters simultaneously for every (n) bits. Corresponding to the number of coincident/noncoincident bits as the compared results, a synchronizing pattern detection circuit 36 judges whether the synchronizing patterns are detected or not. Thus, since the comparison is performed simultaneously for every (n) bits, the frequency of an internal operating clock can be reduced into 1/n in comparison with the conventional frequency. |
