| 摘要 |
PURPOSE:To increase the degree of freedom of evaluation and a test by reading out a program written in a RAM with a test signal and placing a central controller in operation. CONSTITUTION:A unidirectional gate circuit 8 which is enabled to transfer data by the test signal and a ROM timing signal and a bidirectional gate circuit 6 which is enabled to transfer data by the inverted signal of the test signal and a RAM timing signal are provided between a CPU 3 and a RAM 1, and a unidirectional gate circuit 7 which is enabled to transfer data by the inverted signal and the ROM timing signal interposed between the CPU 3 and ROM 2; and the RAM 1 and ROM 2 are connected to the CPU 3 with an address bus 4 and a data bus 5, respectively. |
