| 摘要 |
PURPOSE:To provide a clock extracting system to extract a clock to receive all data from input data and to transmit the received data without being affected by jitter included in the input data. CONSTITUTION:The system is provided with a 1st PLL circuit 1 worked to let a data reception circuit 2 receive each input data, a 2nd PLL circuit 6 worked to let a data transmission circuit 3 transmit received data to a line, and the 1st PLL circuit 1 extracts a 1st clock with a shorter delay time for each input data based on each input data, transmits the clock to the data reception circuit 2, the 2nd PLL circuit 6 extracts a 2nd clock whose delay time for the data is longer than the above-mentioned delay time based on the 1st clock outputted from the 1st PLL circuit 1 and transmits the clock to the data transmission circuit 3. |
