| 摘要 |
PURPOSE:To make it possible simplify a control system and record and reproduce stably signals effectively, by forming and using a simple synchronizing signal. CONSTITUTION:The first block is formed with a data signal of plural word, a one- word parity signal, a one-word error check signal, and one-word information consisting of a synchronizing signal and a control signal, and plural first blocks are collected to form the second block. The output of multiplexer 11 multiplexed in time division is converted to a digital data signal at a prescribed sampling period by A/D converter 12, and a parity signal is added to this data sighal by parity adding circuit 13, and these signals are written in memory 14 and are subjected to the interleave processing. Adder 18 inserts output signals of control signal generating circuit 15 and check signal generating circuit 16 to the data region. Meanwhile, synchronizing signal generating circuits 21 and 22 generate the first and the second synchronizing signals of signal patterns different from each other, and switch circuit 23 selects the signal of circuit 21 and the synchronizing signal of circuit 22 during the first block signal formation and the rest period respectively. Adder 24 inserts selectively the control signal to the beginning of the first block of the sequence added by adder 20. |
