| 摘要 |
An output buffer circuit (10,11) is protected by a short circuit protection circuit (12) from short circuit conditions at the output by detecting occurrence of a short circuit condition of the output (VOUT) shorted to either the high or low potential power rails (VCC, GND) and by tristating the output buffer circuit upon detecting the short circuit condition. Detection of a short circuit condition is accomplished by sensing and comparing the respective states of signals at the input (VIN) and output (VOUT) and detecting occurrence of an out of state condition between the input and output. If the out of state condition is sensed for a sensing time delay period (tC1, tC2) longer than characteristic propagation delay times (tpHL, tpLH), a short circuit sensing signal (VLO, VHI) is generated. Tristating the output buffer circuit is accomplished by logically processing the short circuit sensing signal (VLO, VHI), generating a short circuit tristate enable signal (SOEB), and coupling the short circuit tristate enable signal (SOEB) to a tristate enable circuit input (14) of a tristate enable circuit (10, 11) for tristating the output buffer circuit. The sensing time delay period is achieved by charging an integrating capacitor (C1, C2) in a sensing signal circuit (21, 22). The sensing signal circuit is reset after detecting occurrence of a short circuit condition at the output. Resetting is delayed for a reset time delay period (tC3) substantially greater than the sensing time delay period (tC1, tC2). The reset time delay period is measured by discharging a reset delay capacitor (C3). The short circuit sensing sequence is then repeated.
|
