| 摘要 |
PURPOSE:To extract an output digital signal phase-locked with an input digital signal by providing a frequency voltage conversion circuit, a voltage controlled circuit and a voltage controlled filter in place of a loop filter to the circuit. CONSTITUTION:An input digital signal S3 is inputted to a phase comparator 7 and a frequency voltage conversion circuit 1. The circuit 1 converting an input clock frequency into a predetermined voltage signal counts clock frequencies and outputs a voltage S15 corresponding to the count. The voltage S15 or a coded signal inputted to a voltage controlled circuit 2 is converted into a control voltage S16 for a loop filter. A voltage controlled filter 3 when it is formed by an LC circuit adopts a varactor diode for the capacitor C receives the voltage S16 to transit a pass band of the loop filter to a desired frequency band. The loop filter is the phase locked loop eliminating a high frequency signal of a phase difference signal S7 to a VCO 9 without mis-phase locking and outputs a reference clock signal S9 synchronously with the signal S8. |
