| 摘要 |
<p>PURPOSE:To speed up the reading of a NAND cell type EEPROM without selection gate on the drain side. CONSTITUTION:The drains of memory cells M11, M12 on the bit line BL side out of memory cells M11 to M41, M12 to M42 constituting NAND cells (NAMD1, 2) are directly connected to a bit line BL without being passed through a selection gate and the sources of the memory cells M41, M42 are connected to source lines through section gates S1, S2. In the NAND cell having a selected memory cell in a data reading mode, 0V is applied to a selected word line and Vcc is applied to other non-selected word lines. In the non-selected NAND cell sharing the bit line with the NAND cell having the selected memory cell, voltage smaller than the threshold voltage of a memory cell set up at the time of erasing is impressed to the word line of at least one memory cell in the non-selected NAND cell and OV is applied to other non-selected word lines.</p> |
