| 摘要 |
<p>PURPOSE:To provide a control circuit for an FIFO memory not requiring a special monitor circuit for a write clock in the data replacement circuit employing the FIFO memory. CONSTITUTION:A write clock 12 and a replacement clock 14 are clocks whose frequency is coincident but whose phases are different. When data written in an FIFO memory 1 reaches an output stage, a read enable signal 16 is outputted from the FIFO memory, an N-stage shift register 2 shifts the replacement clock by N-bits, and the supply and its stop of the replacement clock are controlled by a gate 3 based on the output of the shift register 2. Thus, a FIFO read clock 15 is fed to the FIFO memory in N-bits after the read of the FIFO memory is enable.</p> |
