| 摘要 |
A row redundancy circuit for repairing a defective cell of a memory cell array in a semiconductor memory device comprises an address selector (300) for receiving three address bits designating the defective cell to selectively output one of the three address bits. A fuse box (100) stores the information of the remaining address bits except the selected bit output by the address selector, and at least one redundant decoder (200, 200A) decodes the output signals of the address selector and fuse box. By this means it is possible to replace pairs of adjacent faulty (eg: shorted) word lines where the addresses of the two lines differ in the first, second and/or third least significant bit positions. <IMAGE> |
