发明名称 MANUFACTURE OF PACKAGE FOR CONTAINING SEMICONDUCTOR CHIP
摘要 <p>PURPOSE:To provide a method for manufacturing a package for containing a semiconductor chip in which plated metal layers can be simultaneously connected to surfaces of all outer lead terminals without branching a pattern for leading out a metallized wiring layer. CONSTITUTION:All metallized wiring layers 7 brazed with an outer lead terminal 8 provided on an insulating board l are commonly connected by a metal thin film 5a to become a thin film wiring layer 5, and then a plated metal layer 9 is connected to the outer surface of the terminal 8.</p>
申请公布号 JPH05235231(A) 申请公布日期 1993.09.10
申请号 JP19920036085 申请日期 1992.02.24
申请人 KYOCERA CORP 发明人 NINOMIYA YUKIO
分类号 C25D7/12;H01L23/12;H01L23/50;(IPC1-7):H01L23/50 主分类号 C25D7/12
代理机构 代理人
主权项
地址
您可能感兴趣的专利