摘要 |
In a multi-series inverter arrangement comprising a DC circuit (11, 12, 13) including a neutral point output terminal and a multi-series inverter including three series connections of first through fourth GTOs (S1, S2, S3, S4), each connected in parallel with the DC circuit, the juncture of the first and second GTOs (S1, S2) and the juncture of the third and fourth (S3, S4) GTOs being connected to the neutral point output terminal via respective clamping diodes (CD1, CD2) and the first and third GTOs (S1, S3) and the second and fourth GTOs (S2, S4) being on and off controlled each other in a conjugate relationship, individual gate driving circuits (E1H, R2, SW1H, E1W, R1, SW1W) for the second and third GTOs (S2, S3) being designed to provide a larger gate current (IFG1, IFG2), in particular, a larger wide width gate forward current (IFG2) to the corresponding GTOs (S2, S3) than that provided by individual gate driving circuits (E1, R1, R2, C, SW1) for the first and fourth GTOs (S1, S4) to the corresponding GTOs (S1, S4). <IMAGE> |