发明名称 PHASE ADJUSTING CIRCUIT FOR HIGH-SPEED RECEIVED SIGNAL
摘要 <p>PURPOSE:To automatically adjust the phases of received data and a clock signal. CONSTITUTION:This circuit is equipped with a connector 101 for the received data, a connector 102 for a received clock, a delay element part 103, a reception part 104 which retimes the received data, a frame synchronism detection part 105 which detects frame synchronism from the data signal from the reception part 104, a frame synchronism decision part 106 which outputs a switching request signal for a delay element unless the frame synchronism is detected within a specific time, and a selector part 107 which receives the switching request signal for the delay element and switches the delay element selected by the delay element part 103 to another delay element; and the data signal and clock signal are automatically put in phase with each other.</p>
申请公布号 JPH05219040(A) 申请公布日期 1993.08.27
申请号 JP19920019984 申请日期 1992.02.05
申请人 FUJITSU LTD 发明人 SHIRAKAWA TAKAHIRO
分类号 H04J3/06;H04L7/027 主分类号 H04J3/06
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