发明名称 Method of forming a stacked capacitor with striated electrode
摘要 A method of forming a capacitor on a semiconductor wafer includes: a) in a dry etching reactor, selectively anisotropically dry etching a capacitor contact opening having a minimum selected open dimension into an insulating dielectric layer utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component, the flow rate of the bombarding component significantly exceeding the flow rate of the reactive component to effectively produce a capacitor contact opening having grooved striated sidewalls and thereby defining female capacitor contact opening striations; b) providing a layer of an electrically conductive storage node material within the striated capacitor contact opening; c) removing at least a portion of the conductive material layer to define an isolated capacitor storage node within the insulating dielectric having striated sidewalls; d) etching the insulating dielectric layer selectively relative to the conductive material sufficiently to expose at least a portion of the external male striated conductive material sidewalls; and e) providing conformal layers of capacitor dielectric and capacitor cell material atop the etched conductive material and over its exposed striated sidewalls. The invention also includes a stacked capacitor construction having an electrically conductive storage node with upwardly rising external sidewalls. Such sidewalls have longitudinally extending striations to maximize surface area and corresponding capacitance in a resulting construction.
申请公布号 US5238862(A) 申请公布日期 1993.08.24
申请号 US19920854435 申请日期 1992.03.18
申请人 MICRON TECHNOLOGY, INC. 发明人 BLALOCK, GUY;WALD, PHILLIP G.
分类号 H01L21/02;H01L21/8242;H01L27/108 主分类号 H01L21/02
代理机构 代理人
主权项
地址
您可能感兴趣的专利