| 摘要 |
PURPOSE:To eliminate jitter in a clock in the steady-state, to extend the locking range only with a revision of a phase difference comparison discrimination circuit and a decode circuit and to limit the included jitter to a range being + or -1/2 of the clock signal. CONSTITUTION:A phase difference comparing discrimination circuit 104 obtains a phase difference between a Q output of a D flip-flop group 102 and an edge detection signal. A decode circuit 103 decides a D input of the D flip-flop to adjust the phase based on the Q output of the D flip-flop group 102 and a phase difference comparison signal. The digital PLL is established by decoding the Q output of the D flip-flop group 102 so as to be at a required timing. In this case, a timing adjustment signal generated by an edge detection circuit 101 is used to eliminate jitter in the steady-state by using one output after the edge is detected and taking into account a discrimination timing and the included jitter is limited to a + or -1/2 range of the clock signal. |
