发明名称 BIT RATE COUNTER CIRCUIT
摘要 <p>PURPOSE:To obtain average compression data quantity with simple circuit configuration. CONSTITUTION:Code length data ROMs 11, 12 and an adder 13 obtain code length data representing a code length of an unequal length code corresponding to a video data signal. Zero comparators 16, 17 detect a zero of the video data signal and output a zero value detection signal. Zero counters 21, 22 count the number of times of production of the zero detection signal and output zero occurrence data representing a zero production value. A block counter 25, latch circuits 26, 27 and an adder 28 latch and output the zero occurrence data in the unit of the number of prescribed data tentatively. A subtractor 30 subtracts zero number data from code length data in the unit of the number of data to output subtraction data. An integration adder 31 integrated subtraction data and outputs the integration data. The latch circuit 33 latches the integration data in the unit of a prescribed frame as mean compression data quantity.</p>
申请公布号 JPH05207436(A) 申请公布日期 1993.08.13
申请号 JP19920012780 申请日期 1992.01.28
申请人 NEC CORP;NIPPON HOSO KYOKAI <NHK> 发明人 KATSUBE RYOJI;ITO NOBUYOSHI;OKAMURA HIROSHI
分类号 H04N19/00;H04N19/42;H04N19/423;H04N19/85;H04N19/91 主分类号 H04N19/00
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