发明名称 PROGRAMMABLE CONTROLLER
摘要 <p>PURPOSE:To output results of parallel processing to a controlled system and to improve a processing speed through simple constitution by providing a common control circuit which allows plural processors to perform processing synchronously in parallel according to assigned programs. CONSTITUTION:A processing unit consists of a master processing unit 3 and a slave processing unit 4, and an instruction memory 1 and an input/output device 2 which inputs and oututs a process signal are used in common. Those processors 3 and 4 are provided with processors 81 and 82 connected to the memory 1, operand address memories 61 and 62 cnnected to the processors 81 and 82, and input/output buffers 71 and 72 connected to the processors 81 and 82 and device 2. Further, a port memory 92 is provided between the processors 81 and 82 and a program control part 5 is provided between the processor 81 and memory 1. Then, the processors 81 and 82 execute supplied programs synchronously in parallel and output the results of the processing to the controlled system to increase the processing speed through the simple hardware.</p>
申请公布号 JPS59154564(A) 申请公布日期 1984.09.03
申请号 JP19830028541 申请日期 1983.02.24
申请人 HITACHI SEISAKUSHO KK 发明人 OKAMOTO TADASHI;YAMAOKA HIROMASA
分类号 G06F15/16;G05B19/05;G06F9/00;G06F9/38;G06F9/46;G06F12/00;G06F15/80 主分类号 G06F15/16
代理机构 代理人
主权项
地址