| 摘要 |
A multiplying circuit is able to perform a multiplication of n bitsxn bits at a high speed by increasing the speed of the forming process of the partial products so that the delay time may be inhibited from increasing for a large n, and which can inhibit the chip size from becoming large. A 6-bit multiplier (Y1 to Y6) is divided into bit sets each having plural bits. The thus divided sets are inputted respectively into booth decoders 1A to 1C to generate three-bit interim outputs m1 to m3. On the other hand, partial product generating circuits 2A, 2B and 2C receive a multiplicand X of plural bits to form partial products p1, p2 and p3 respectively by multiplying the multiplicand X with the interim outputs m1, m2 and m3. These partial products p1 to p3 are transformed in a first full adder allay 3 into interim sums r1 and r2. The thus formed interim sums r1 and r2 are added in a second full adder allay 4 with a value. "s" which is prepared by arranging the lowest bits of the interim outputs m1, m2 and m3 by every other bits with "0" therebetween. The thus formed interim sums are defined as r3 and r4. An adder 5 adds up these interim sums r3 and r4 to provide a multiplication output.
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