发明名称 |
dRAM cell and method |
摘要 |
A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel and drain and one capacitor plate are formed essentially vertically in the bulk substrate sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench and isolated from the bulk by an insulating layer. Signal charge is stored on the capacitor material inserted into the trench by an electrical connection of the bulk substrate source to the capacitor material through the insulating layer. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface form the drains. The trenches and cells are formed at the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.
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申请公布号 |
US5225697(A) |
申请公布日期 |
1993.07.06 |
申请号 |
US19920859286 |
申请日期 |
1992.03.26 |
申请人 |
TEXAS INSTRUMENTS, INCORPORATED |
发明人 |
MALHI, SATWINDER S.;POLLACK, GORDON P.;RICHARDSON, WILLIAM F. |
分类号 |
H01L21/225;H01L21/334;H01L21/8242;H01L27/108 |
主分类号 |
H01L21/225 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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