| 摘要 |
PURPOSE:To avoid an inverted phase output caused when the relation of phases of an input clock and a reference pulse is inverted in a clock frequency divider circuit. CONSTITUTION:This circuit is provided with a 1st flip-flop 1 applying 1/2 frequency division to an input clock (a) based on a reference pulse (b), a 1st exclusive OR circuit 6 exclusively ORing an output (d) of the 1st exclusive OR circuit 6 and an inverted signal of the input clock (a) based on the reference pulse, a 3rd flip-flop 7 used to read the output (e) of the 1st exclusive OR circuit 6 with the output of the 2nd flip-flop 3, and a 2nd exclusive OR circuit 8 inverting or noninverting a frequency division output (d) from the 1st flip-flop 1 through the output result (f) of the 3rd flip-flop 7. |
