| 摘要 |
PURPOSE:To enable efficient circuit design by supplying the data required for the code correction of the partial product to an adder after converted into the form equivalent to the data and suitable for the input form of the adder in the initial setting value means. CONSTITUTION:Based on signals prescribing a multiple of the partial product and code, partial product generation circuits PPG 15 to 18 form partial products PP15 to 18 with complementary processing, which are supplied to redundant binary adders BRA 21 to 24 for alogorithm multiplier circuit of Booth. The complementary processing bit to be prescribed by the input form of an initial value setting circuit 20 is converted equivalent into the conversion bit, matching the output form of the initial value setting circuits 20 and the input form of the BRA 21 to 24. The input form and the output form of the BRA 21 to 24 are also matched. The circuit design is performed by repeatedly using the basic circuit in the multiplier circuit of the combinatorial circuit and using the basic circuit in the multiplier circuit of the time-division circuit. |
