DIRECT CONTROLLABLE CACHE MEMORY

摘要

The cache memory for improving the cache hit rate comprises a state machine unit (1) for generating an answer signal responding to a request signal from a CPU to control the cache memory block, a cache control register (2) for providing a dignostic checking mode and the cache memory block (2) for discriminating the cache hit states to perform an cache access. The state machine unit includes a cache block state controller and a cache access controller. The cache memory further includes a trap generator (4) for checking the hardware error to generate a break point trap and an alignment trap.