| 摘要 |
<p>A memory accessing device is connected to a first bus 28 for connecting a first buffer storage unit 23 in a central processing unit 22 and to a second buffer storage unit 24 for accessing at least one of the first buffer storage unit 23 and the second buffer storage unit 24 independently of the central processing unit 22. It comprises an address generating circuit 11 for generating an address according to which at least one of the first buffer storage unit 23 and the second buffer storage unit 24 is accessed, an output control unit 12 for outputting the address to the first bus 28 and for controlling such that the output from the output control unit 12 enters the idle state if the second buffer storage unit 24 issues a request for access to the first buffer storage unit 23 when the memory accessing device obtains a bus use right of the first bus. <IMAGE></p> |
