发明名称 RECEPTION BURST SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To improve the S/N of a PSK reception burst signal and to reduce the bit error. CONSTITUTION:The reception burst synchronizing circuit demodulating a PSK burst signal is provided with a matched filter 1 applying waveform equalization to a reception PSK burst signal subject to distortion on a transmission line, a comparator 2 binary-converting an output subject to waveform equalization with the matched filter 1, a synchronizing signal detection section 3 extracting an NRZ synchronizing signal by one bit from a unique word included in a preamble word of a PSK burst signal outputted from the comparator 2 and a sampling clock extract section 4 measuring a width of a bit pulse of the NRZ synchronizing signal by one bit extracted by the synchronizing signal detection section 3 and generating a sampling clock Sck to sample each bit of an ID code and data in a PSK burst signal in succession to the unique word corresponding to an intermediate point of the bit pulse of the NRZ synchronizing signal.
申请公布号 JPH05122214(A) 申请公布日期 1993.05.18
申请号 JP19910306737 申请日期 1991.10.25
申请人 NEC CORP 发明人 TAKE YOSHIHIKO
分类号 H04L7/00;G01S1/08;G01S1/54;H04L7/10;H04L27/22 主分类号 H04L7/00
代理机构 代理人
主权项
地址