发明名称 |
Instruction generator architecture for a video signal processor controller |
摘要 |
A synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and is capable of real-time digital processing of video signals. In video applications a data input control circuit including a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit is provided.
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申请公布号 |
US5210836(A) |
申请公布日期 |
1993.05.11 |
申请号 |
US19890421500 |
申请日期 |
1989.10.13 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
CHILDERS, JIM;REINECKE, PETER;CHUNG, MOO-TAEK;MIYAGUCHI, HIROSHI |
分类号 |
F02B75/02;G06F15/80;G06T1/20 |
主分类号 |
F02B75/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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