| 摘要 |
<p>PURPOSE:To simplify the configuration of a multiplexer circuit multiplexing a television signal subjected to variable length coding through parallel processing. CONSTITUTION:Television signals subjected to 3-phase parallel expansion are subjected to variable length coding by variable length coders 11, 21, 31, variable length coding data strings D1, D2, D3 are respectively inputted to delay circuits 12, 22, 32, in which the data are delayed by one processing unit time T. A multiplexer circuit 101 extracts and multiplexes data for each of n-bit from the delayed data strings D20, D21, D22. Furthermore, the total sum WL of a data length of the data strings D1, D2, D3 obtained by variable length coders 11, 21, 31 is obtained and a write clock control signal S20 of multiplexed data D23 to a buffer memory 102 is generated by a write clock control circuit 104 from the WL.</p> |
