LAYOUT METHOD FOR SEMICONDUCTOR DEVICE,申请号JP19910271433-传众专利搜索

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发明名称	LAYOUT METHOD FOR SEMICONDUCTOR DEVICE
摘要
申请公布号	JPH05108760(A)	申请公布日期	1993.04.30
申请号	JP19910271433	申请日期	1991.10.18
申请人	FUJITSU LTD;FUJITSU VLSI LTD	发明人	YONEDA TAKASHI
分类号	H01L21/82;G06F17/50	主分类号	H01L21/82
代理机构		代理人
主权项
地址

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