| 摘要 |
<p>PURPOSE:To inexpensively obtain the device having high reliability by latching necessary data at a prescribed timing conforming to a frame of input data, further delaying this latch data for a prescribed time and latching it, and selecting an abstract object in accordance with a phase difference of an input timing to a latch timing. CONSTITUTION:Input data 10 is subjected to S/P conversion by a shift register 1. A latch timing generating circuit 6 receives an input clock 11 and a frame synchronizing signal 12, and generates a latch signal for a latch 2 and a latch signal for a latch 3 delayed by a half frame period portion from the former. A selector control circuit 8 monitors a latch timing and a load timing by a synchronizing phase detecting part 8A, and in the case both of them are too near, a selecting signal output of a switching signal generating part 8B is switched, and an output of the latch 2 or 3 is outputted as serial data 13 subjected to phase absorption and speed conversion. In such a way, the device having high reliability can be constituted at a low cost.</p> |
