| 摘要 |
<p>Method (V) for verifying the post-erasure contents of an erasable permanent memory embracing an instruction register (RC) and an address register, comprising a first step (V1) of writing an erasure-verification instruction word into this instruction register (RC), followed by a second step (TV) of timing-out of predetermined duration (T2). The first step (V1) of writing the instruction word initiates the following sequence: - opening of the address register, - presentation of a first address, - iterative looping (B) for reading the contents at the address concerned and incrementation of this address until the whole of the memory has been verified, and - closure of the address register. The verification device for operating this method comprises logic means for generating an address-transfer enable signal applied to the address register, from a fast-erasure verification signal and from an address clock signal. Use for the optimisation of procedures for erasure of FLASH EPROM memories. <IMAGE></p> |
